Spin coating for maximum fill characteristic yielding a planarized thin film surface

ABSTRACT

A method for spinning a material onto a semiconductor device structure so as to substantially fill recesses formed in a surface of the semiconductor device structure and to impart the material with a substantially planar surface and semiconductor device structures formed thereby. The thickness of the material covering the surface is less than the depth of the recesses. The surface may remain substantially uncovered by the material.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a divisional of application Ser. No.09/542,783, filed Apr. 4, 2000, pending.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to methods for filling containers,trenches, or other recesses of semiconductor device structures duringfabrication thereof. Particularly, the present invention relates to theuse of spin coating techniques to fill containers, trenches, and otherrecesses of semiconductor device structures. As a specific example, thepresent invention relates to a method for masking hemispherical grain(HSG) silicon-lined containers of a stacked capacitor structure tofacilitate removal of HSG silicon from the surface of a semiconductordevice structure including the stacked capacitor structure.

[0004] 2. Background of Related Art

[0005] Conventionally, spin-on processes have been used to applysubstantially planar layers of material to the surfaces of semiconductordevice structures being fabricated upon a wafer of semiconductormaterial (e.g., a silicon, gallium arsenide, or indium phosphide wafer)or other semiconductor substrate (e.g., a silicon on insulator (SOI),silicon on glass (SOG),silicon on ceramic (SOC), silicon on sapphire(SOS), or other similar substrate). Consequently, while the portions ofa spun-on layer of material over substantially horizontal structures maybe substantially planar, the layer of material may not substantiallyfill or conform to the numerous, minute recesses formed in thesemiconductor device structure.

[0006] For example, when it is desirable to mask a container, trench, orother recess of a semiconductor device structure without masking thesurface of the semiconductor device structure to which the container,trench, or other recess opens, a mask material is typically applied tothe surface of the semiconductor device structure, such as by use ofknown spin-on processes. As an example, FIG. 1 illustrates thefabrication of a stacked capacitor structure 10 with conductively dopedHSG silicon 16-lined containers 14. As it is necessary to remove HSGsilicon 16 from a surface 12 of an electrical insulator layer 11 (e.g.,borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), orborosilicate glass (BSG)) of stacked capacitor structure 10 to preventelectrical shorting between adjacent containers 14, mask material 18′ isintroduced into containers 14 to facilitate removal of HSG silicon 16from surface 12.

[0007] While conventional spin-on processes will force some of the maskmaterial into containers 14, trenches, or other recesses, theseprocesses typically result in the formation of a relatively thick, butnot necessarily planar layer of mask material 18′ over surface 12. Dueto various factors, including the surface tension of mask material 18′and the centrifugal forces applied to mask material 18′ during thespin-on process, mask material 18′ tends to migrate out of the smallrecesses (e.g., containers 14) formed in surface 12. Thus, the thicknessof mask material 18′ within a container 14, trench, or other recess maynot be significantly greater than the thickness of mask material 18′covering surface 12, leaving containers 14 partially unfilled. Once thelayer of material has been dispensed onto the semiconductor devicestructure, it is solidified or cured, such as by known photographic orsoft bake processes.

[0008] In order to reduce the thickness of the layer of mask materialcovering the surface of the semiconductor device structure withoutsubstantially decreasing the thickness of the layer of mask materialwithin the recesses, chemical-mechanical planarization (CMP) processes,such as chemical-mechanical polishing techniques, are typicallyemployed. The use of CMP processes is, however, somewhat undesirablesince such processes are known to create defects in the surface of thesemiconductor device structure. CMP processes are also known to leavedebris, or contaminants, which may be trapped in defects in the surfaceof the semiconductor device structure and which may subsequently causeelectrical shorting of a fabricated semiconductor device. For example,if CMP processes are used to remove mask material and at least part of aconductively doped HSG silicon layer from an insulator at the surface ofa stacked capacitor structure, conductive silicon particles may betrapped in defects in the surface of the insulator and subsequentlycause electrical shorting between adjacent containers of the stackedcapacitor. These potentially damaging contaminants may remain even whena chemical removal process, such as a wet or dry etch, follows the CMPprocess.

[0009] Alternatively, a photoresist may be used as the mask material.Patterning of the photoresist requires several steps in which equipmentmust be precisely aligned with features, such as the containers of astacked capacitor structure, fabricated on the semiconductor substrate.Additional handling of the semiconductor device structure is alsorequired when a photoresist is used to mask containers, trenches, orother recesses formed in a semiconductor device structure, which issomewhat undesirable.

[0010] Moreover, when conventional blanket deposition techniques areused to fill the recesses of a semiconductor device structure with amaterial (e.g., to fill the trenches of a shallow trench isolationstructure with an electrical insulator material and to fill dualdamascene trenches with a conductive material), the material typicallyforms a nonplanar layer over the semiconductor device structure. Suchmaterial layers typically include valleys located over recesses in theunderlying semiconductor device structure and peaks located over otherregions of the semiconductor device structure. Chemical-mechanicalplanarization is an example of a conventional technique for removingsuch materials from the surface of a semiconductor device structurewhile leaving these materials within the recesses of the semiconductordevice structure. As chemical-mechanical planarization processestypically employ an abrasive pad to mechanically planarize structures,however, the peaks of the material layer may break off in larger thandesired pieces and subsequently scratch the surface of the semiconductordevice structure, forming defects therein.

[0011] The art does not teach a semiconductor device structure thatincludes a nonchemical-mechanical planarized material layer thatsubstantially fills a container, trench, or other recess formed in thesemiconductor device structure and which does not substantially coverthe remainder of a surface of the semiconductor device structure orwhich includes only a relatively thin layer of material over theremainder of the surface. The art also fails to teach a method forforming a material layer with these features. In addition, the art lacksteaching of a method for reducing the likelihood that peaks of anonplanar layer of material will damage a surface of a semiconductordevice structure during subsequent planarization of the layer ofmaterial.

SUMMARY OF THE INVENTION

[0012] The present invention includes semiconductor device structureswith substantially planar surfaces. The semiconductor device structuresalso include containers, trenches, or other recesses that are filledwith a material. The material may also cover adjacent surfaces of thesemiconductor device structures. If the material covers surfaces of thesemiconductor device structures, the thickness of the material coveringthe surface is less than the depth of the containers, trenches, or otherrecesses that are substantially filled with material. Preferably, thethicknesses of material covering the surfaces of the semiconductordevice structures are less than about half the depth of the containers,trenches, or other recesses. The surfaces of the material or materialsthat fill the recesses and that may cover the surfaces of thesemiconductor device structures have not, however, beenchemical-mechanical planarized to achieve the reduced depth of materialoutside of the recesses.

[0013] In one embodiment of the present invention, the semiconductordevice structure includes a stacked capacitor structure with a layer ofelectrically insulative material, or insulator layer, and at least onecontainer recessed or formed in the insulator layer. The insulator layerincludes a substantially planar surface, which is referred to herein asthe exposed surface of the insulator layer. A layer of electricallyconductive material covers the surface of the insulator layer and linesthe at least one container. By way of example, the electricallyconductive material may be conductively doped hemispherical grain (HSG)silicon. As the stacked capacitor structure would electrically short ifthe conductive material remained on the surface of the insulator layerbetween adjacent containers, for the stacked capacitor to functionproperly, the conductive material must be removed from the surface ofthe insulator layer prior to completing fabrication of the stackedcapacitor but remain within the containers. Thus, this embodiment of thesemiconductor device structure includes a substantially planar surfacewith a non-chemical-mechanical planarized quantity of mask materialsubstantially filling the at least one container. While the maskmaterial may cover regions of the layer of conductive material overlyingthe surface of the insulator layer, it is preferred that these regionsare substantially uncovered by mask material. If mask material doesoverlie these regions of the layer of conductive material, the thicknessof the mask material overlying these regions is less than the depth ofthe at least one container. Preferably, the thickness of the maskmaterial over these regions of the layer of conductive material is lessthan about half the depth of the at least one container.

[0014] The mask material may be applied to the semiconductor devicestructure by known processes and is spread across the surface of thestacked capacitor structure so as to substantially fill the at least onecontainer while leaving a thinner, or no, material layer over regions ofthe layer of conductive material that overlie the surface of theinsulator layer. For example, the mask material may be spread across thesurface of the stacked capacitor structure by use of spin-on techniques,wherein the mask material is applied at a first speed, the rate ofspinning is decreased to a second speed at which the mask material ispermitted to at least partially set up, then the rate of spinning isgradually increased, or ramped up, to a third speed at which a desired,reduced thickness of mask material covering the surface may be obtained.The rate at which the stacked capacitor structure is spun may again bedecreased to permit the mask material to further set. An edge bead ofmask material may then be removed from the stacked capacitor structureand the stacked capacitor structure spun once again to remove solventsfrom the mask material.

[0015] In another embodiment of the semiconductor device structure, amask is disposed over a shallow trench isolation (STI) structure thatincludes a semiconductor substrate with a substantially planar surfaceand shallow trenches recessed, or formed, in the semiconductorsubstrate. The semiconductor device structure has a substantially planarsurface, without requiring chemical-mechanical planarization of thesurface of the mask. If material of the mask covers the surface of thesemiconductor substrate, the thickness of mask material thereover issignificantly less than the depths of the shallow trenches. Preferably,the thickness of mask material covering the surface of the semiconductorsubstrate is less than about half the depths of the trenches. Morepreferably, the surface of the semiconductor substrate remainssubstantially uncovered by the mask material. The present embodiment ofthe semiconductor substrate may also include conductively doped regionscontinuous with the surface and located between the trenches formed inthe semiconductor substrate.

[0016] The shallow trench isolation structure may be formed by knownprocesses. The mask may be formed by applying a quantity of maskmaterial to the shallow trench isolation structure and spreading themask material over the surface so as to substantially fill each trenchthereof. As an example of the manner in which mask material may bespread across the shallow trench isolation structure, the mask materialmay be spun across the semiconductor substrate at a first speed, therate of spinning decreased to a second speed to permit the mask materialto at least partially set up while remaining in the trenches, then therate of spinning gradually increased, or ramped up, to a third speed atwhich a desired, reduced thickness of mask material covering the surfacemay be obtained. The rate at which the shallow trench isolationstructure is spun may again be decreased to permit the mask material tofurther set. An edge bead of mask material may then be removed from theshallow trench isolation structure and the shallow trench isolationstructure spun once again to remove solvents from the mask material.Conductively doped regions of the semiconductor substrate may be formedby exposing the substrate and mask material to a conductivity dopant.The regions of the semiconductor substrate that remain uncovered or thatare covered with thinner layers of the mask material (e.g., the surfaceof the semiconductor substrate) are implanted with the conductivitydopant while regions of the semiconductor substrate that are coveredwith thicker layers of the mask material (e.g., regions of thesemiconductor substrate beneath the trenches) remain substantiallyundoped.

[0017] Another embodiment of a semiconductor device structure accordingto the present invention includes a surface with one or more recessesformed therein and a layer of a first material substantially fillingeach recess and at least partially covering the surface. The layer offirst material has a nonplanar surface and may include a valley locatedsubstantially over each recess in the semiconductor device structure andone or more peaks located substantially over the surface of thesemiconductor device structure. A second material disposed over thelayer of first material at least partially fills each of the valleysformed in the layer of first material. The second material has asubstantially planar surface that is not further planarized followingformation thereof.

[0018] By way of example, the semiconductor device structure may be ashallow trench isolation structure including a semiconductor substratewith a substantially planar surface and trenches recessed, or formed, inthe semiconductor substrate. The trenches are filled with a first,electrically insulative material, which is preferably a low dielectricconstant, or “low-k”, material, such as a high density plasma (HDP)silicon oxide, or HDP oxide. HDP oxide or another insulative materialmay be disposed into the trenches by way of known processes, such aschemical vapor deposition (CVD) processes. As the processes that areused to fill the shallow trenches with the first, insulative materialare typically blanket deposition processes, the insulative material mayalso cover the surface of the semiconductor substrate. The surface of alayer of the first, insulative material blanket deposited over asemiconductor substrate with trenches formed therein is nonplanar.

[0019] As another example of the deposition of a first material over asemiconductor device structure, each recess of the semiconductor devicestructure may be a dual damascene type trench substantially filled witha first, conductive material. The first, conductive material may bedisposed into each dual damascene trench of the semiconductor devicestructure by known processes, such as physical vapor deposition (PVD)(e.g., sputtering) or chemical vapor deposition techniques. Since theseprocesses typically form a layer of material that blankets substantiallythe entire semiconductor device structure, the first, conductivematerial may also cover the surface of the semiconductor devicestructure. When blanket deposited over a semiconductor device structurewith trenches formed therein, such layers typically have nonplanarsurfaces.

[0020] The second material is preferably a stress buffer material thatfacilitates planarization of the layer of insulative material withoutcausing substantial defects in either the insulative material or in thesurface of the underlying semiconductor substrate. Exemplary materialsthat are useful as the stress buffer include resins and polymers thatmay be applied by way of spin-on techniques. The stress buffer has asubstantially planar surface and preferably fills the valleys in thelayer of insulative material without substantially covering the peaksthereof.

[0021] After the stress buffer material is applied to the semiconductordevice structure, it may be spread across the surface of thesemiconductor device structure by a spin-on technique that includesspinning the semiconductor device structure at a first speed, decreasingthe rate of spinning to a second speed at which the material of thestress buffer within the valleys is permitted to at least partially set,then gradually increasing, or ramping up, the rate of spinning to athird speed at which a desired thickness of stress buffer materialcovering the surface may be obtained. The rate at which thesemiconductor device structure is spun may again be decreased to permitthe stress buffer material to further set. An edge bead of stress buffermaterial may then be removed from the semiconductor device structure andthe semiconductor device structure spun once again to remove solventsfrom the stress buffer material.

[0022] If portions of the first material layer protrude through thesecond material, all or part of the first material layer may be removedwith selectivity over the second material by known processes, such as byuse of wet or dry etchants. The protruding portions of the firstmaterial layer may be partially removed until a surface of the firstmaterial is in substantially the same plane as a surface of the secondmaterial. The first and second materials may then be substantiallyconcurrently removed from over the surface of the semiconductor devicestructure by known chemical-mechanical planarization or etchingprocesses. Following the removal of the first and second materials, thesurface of the first material remaining in each recess is preferablysubstantially flush with the surface of the semiconductor devicestructure. Alternatively, the first material can be selectively removedto expose the surface of the semiconductor device structure, then thesecond material removed therefrom.

[0023] If the semiconductor device structure has a substantially planarsurface after the second material is disposed thereon, the first andsecond materials may be substantially concurrently removed by knownchemical-mechanical planarization or etching processes to provide asemiconductor device structure with the first material substantiallyfilling the recesses thereof and having a substantially planar surface.

[0024] Other features and advantages of the present invention willbecome apparent to those of skill in the art through consideration ofthe ensuing description, the accompanying drawings, and the appendedclaims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1 (Prior Art) is a cross-sectional representation of astacked capacitor structure with a surface and containers lined withconductively doped hemispherical grain polysilicon and including aconventionally spun-on layer of mask material thereover;

[0026]FIG. 2 is a cross-sectional representation of a stacked capacitorstructure including a layer of mask material substantially filling thecontainers thereof and having a substantially planar surface;

[0027]FIG. 3 is a cross-sectional representation of the stackedcapacitor structure of FIG. 2, depicting the mask material andconductively doped hemispherical grain polysilicon removed from over thesurface, the containers remaining substantially filled with maskmaterial;

[0028]FIG. 4 is a cross-sectional representation of the stackedcapacitor structure of FIG. 3 with the mask material removed from thecontainers;

[0029]FIG. 5 is a cross-sectional representation of a shallow trenchisolation structure including a semiconductor substrate with a surfaceand trenches formed in the surface and a layer of mask material thatsubstantially fills the trenches and has a substantially planar surface;

[0030]FIG. 6 is a cross-sectional representation of the shallow trenchisolation structure of FIG. 5 that schematically illustrates doping ofportions of the semiconductor substrate that are continuous with thesurface and laterally adjacent the trenches without doping of portionsof the semiconductor substrate beneath the trenches;

[0031]FIG. 7 is a cross-sectional representation of a shallow trenchisolation structure including a nonplanar layer of electricallynonconductive material filling the trenches and overlying the surfacethereof and a layer of stress buffer material with a substantiallyplanar surface filling recesses in and overlying the layer ofelectrically nonconductive material;

[0032]FIG. 8 is a cross-sectional representation of a variation of theshallow trench isolation structure of FIG. 7, which includes stressbuffer material with a substantially planar surface partially fillingrecesses in the layer of electrically nonconductive material;

[0033]FIG. 9 is a cross-sectional representation of the shallow trenchisolation structure of FIG. 8, depicting the layer of electricallynonconductive material partially removed to form a substantially planarsurface flush with the surfaces of the stress buffer material in therecesses of the layer;

[0034]FIG. 10 is a cross-sectional representation of the shallow trenchisolation structure of FIG. 9, illustrating stress buffer materialdisposed at least partially over the electrically nonconductive materialremaining in the trenches;

[0035]FIG. 11 is a cross-sectional representation of the shallow trenchisolation structures of FIGS. 7 and 10, depicting the electricallynonconductive material within the trenches as having a substantiallyplanar surface that is substantially flush with the surfaces of thesemiconductor substrates of the shallow trench isolation structures;

[0036]FIG. 12 is a cross-sectional representation of a semiconductordevice structure including dual damascene trenches recessed in a surfacethereof, a nonplanar layer of conductive material substantially fillingthe trenches and covering the surface of the semiconductor devicestructure, and a layer of stress buffer material with a substantiallyplanar surface disposed over and filling recesses in the layer ofconductive material;

[0037]FIG. 13 is a cross-sectional representation of a variation of thesemiconductor device structure of FIG. 12, which includes stress buffermaterial with a substantially planar surface only partially fillingrecesses formed in the layer of conductive material;

[0038]FIG. 14 is a cross-sectional representation of the semiconductordevice structure of FIG. 13, depicting the layer of conductive materialpartially removed to form a substantially planar surface flush with thesurfaces of the stress buffer material in the recesses of the layer;

[0039]FIG. 15 is a cross-sectional representation of the semiconductordevice structure of FIG. 14, illustrating stress buffer materialpartially disposed at least partially over the conductive materialremaining in the trenches; and

[0040]FIG. 16 is a cross-sectional representation of the semiconductorstructures of FIGS. 12 and 15, depicting the conductive material withinthe trenches as having a substantially planar surface that issubstantially flush with the surfaces of the semiconductor devicestructures.

DETAILED DESCRIPTION OF THE INVENTION

[0041] With reference to FIG. 2, a semiconductor device structure, inthis case a stacked capacitor structure 10, incorporating teachings ofthe present invention is illustrated. Stacked capacitor structure 10includes a surface 12 with containers 14 recessed, or formed, in surface12. As illustrated, surface 12 and containers 14 are lined with a layer16 of conductively doped hemispherical grain silicon. Stacked capacitorstructure 10 also includes a mask layer 18 of a polymer material (e.g.,polyimide or photoresist) disposed over layer 16. Mask layer 18substantially fills containers 14 and has a substantially planar exposedsurface 19. The thickness T of portions of mask layer 18 overlyingsurface 12 is less than the depth D of containers 14 and, preferably, isless than about half of depth D.

[0042] Stacked capacitor structure 10, including the conductively dopedhemispherical grain silicon layer 16 thereof, may be fabricated by knownprocesses, such as those disclosed in U.S. Pat. No. 5,663,090, issued toDennison et al. on Sep. 2, 1997, the disclosure of which is herebyincorporated in its entirety by this reference. Mask layer 18 is formedon stacked capacitor structure 10 by dispensing a mask material ontostacked capacitor structure 10 while spinning the substrate bearingstacked capacitor structure 10 relative to an axis perpendicular to aplane of the substrate bearing stacked capacitor structure 10 at a firstspeed, which is preferably an optimum speed for forming a substantiallyhomogeneous film from the mask material. When a substantiallyhomogeneous film of mask material has been formed on stacked capacitorstructure 10, the rate at which stacked capacitor structure 10 is spunis decreased to a second speed. The second speed and the duration atwhich stacked capacitor structure 10 is spun at the second speed permitsthe mask material to flow into and to begin to set within containers 14of stacked capacitor structure 10. The rate of spinning stackedcapacitor structure 10 is then gradually increased, or ramped up, to athird speed, which is maintained until a film of mask material coveringsurface 12 reaches a desired, reduced thickness. The rate at whichstacked capacitor structure 10 is spun may again be reduced to furtherpermit the mask material to set. A bead of the mask material formedaround the periphery of a substrate (e.g., a wafer) including stackedcapacitor structure 10 may be removed by known processes to provide asubstantially planar surface over stacked capacitor structure 10. Thesubstrate including stacked capacitor structure 10 may also be spunagain to begin removing solvents from the mask material. Mask layer 18is then subjected to a soft bake, as known in the art, to substantiallyremove solvents from the mask material.

[0043] By way of example, when ARCH 895 photoresist is used as the maskmaterial, the substrate bearing stacked capacitor structure 10 is spunat a first speed of about 1,000 rpm until a substantially homogeneouslayer is formed (e.g., about one second to about five seconds). Thespinning rate is then decreased to about 100 rpm for a period of aboutfive seconds to about ten seconds to allow the photoresist withincontainers 14 to begin setting. The rate at which stacked capacitorstructure 10 is spun is then gradually increased to a third speed of atleast about 1,500 rpm until the photoresist covering surface 12 reachesa desired, reduced thickness or until the photoresist is substantiallyremoved from surface 12. The spin rate is then decreased again, thistime to about 50 rpm, for a duration of about 19 to about 50 seconds topermit additional setting, or casting, of the photoresist. Suchadditional spinning creates a bead of photoresist near an edge of asubstrate of which stacked capacitor structure 10 is a part. Known edgebead removal techniques are employed to remove this bead from the edgeof the substrate and to provide a substantially planar surface. Anysolvent remaining in the photoresist is then substantially removedtherefrom by gradually increasing the rate at which stacked capacitorstructure 10 is spun to about 5,000 rpm. Mask layer 18 is then subjectedto a known soft bake process, preferably at a temperature of about 100°C. to about 150° C. to substantially remove solvents from thephotoresist.

[0044] Referring now to FIG. 3, once a mask layer 18 with asubstantially planar surface 19 is formed, the portions of mask layer 18and of hemispherical grain silicon layer 16 that are located above aplane of surface 12 are removed from stacked capacitor structure 10. Inorder to reduce or eliminate the creation of potentially contaminatingdebris and of surface defects that may be caused by mechanicalplanarization processes, layers 18 and 16 are removed by known chemicalprocesses, such as dry etch processes or wet etch, or wet dip,processes. For example, mask layer 18 may be selectively removed by useof a known resist strip, then layer 16 removed from surface 12 with awet etchant that removes silicon with selectivity over the portions ofmask layer 18 remaining in containers 14 and over an underlyingdielectric layer 15. As another example, layers 18 and 16 may besubstantially concurrently removed with an etchant or combination ofetchants that will remove mask layer 18 and hemispherical grain siliconlayer 16 at substantially the same rates. Mask material remaining incontainers 14 may then be removed by known processes, such as the use ofknown wet or dry strip materials (e.g., an ammonium hydroxide (NH₄OH)dry strip known in the art as a “piranha” strip when the mask materialis ARCH 895 or a similar photoresist). This process provides a stackedcapacitor structure 10 with conductively doped hemispherical grainsilicon 16-lined containers 14 recessed in a substantially defect-andcontaminant-free surface 12 of structure 10 and dielectric layer 15, asshown in FIG. 4. Stacked capacitor structure 10 shown in FIG. 4 may thenbe processed as known in the art to fabricate a finished stackedcapacitor.

[0045] Turning now to FIGS. 5 and 6, another embodiment of asemiconductor device structure, in this instance a shallow trenchisolation structure 20, incorporating teachings of the present inventionis illustrated. FIG. 5 depicts a shallow trench isolation structure 20that includes a semiconductor substrate 21 formed from silicon, galliumarsenide, indium phosphide, or another suitable semiconductor material,and which may be in the form of a wafer or another substrate, such as asilicon-on-glass, silicon-on-sapphire, silicon-on-ceramic, or othersilicon-on-insulator type substrate. Semiconductor substrate 21 includesa surface 22 with one or more trenches 24 recessed, or formed, therein.Trenches 24 may be formed in semiconductor substrate 21 by knowntechniques, such as mask and etch processes. Shallow trench isolationstructure 20 also includes a mask layer 28 with a substantially planarsurface 29. Mask layer 28 substantially fills trenches 24 and may alsocover surface 22 of semiconductor substrate 21. As shown in FIG. 5, thethickness T′ of portions of mask layer 28 overlying surface 22 is lessthan the depth D′ of trenches 24. Preferably, thickness T′ is less thanabout half of depth D′. Alternatively, surface 22 may remainsubstantially uncovered by mask layer 28. Mask layer 28 may be formedfrom a photoresist or other polymer by processes the same as or similarto those described previously herein with reference to the fabricationof mask layer 18 illustrated in FIG. 2.

[0046]FIG. 6 illustrates the implantation of a conductivity dopant C,such as a known p-type or n-type conductivity dopant (e.g., phosphorus(P), boron (B), arsenic (As), or antimony (Sb)), into shallow trenchisolation structure 20 through mask layer 28. Conductivity dopant C isprevented from passing through the thicker regions of mask layer 28 intoregions 25 of semiconductor substrate 21 located at the bottoms oftrenches 24. Conductivity dopant C does, however, pass through thinnerareas of mask layer 28 that are located on surface 22 or to exposedareas of surface 22 so as to conductively dope regions 23 ofsemiconductor substrate 21 continuous with surface 22, which regions lielaterally adjacent trenches 24. Once regions 23 have been conductivelydoped, mask layer 28 may be removed from trenches 24 and surface 22 (ifnecessary) to facilitate completion of shallow trench isolationstructure 20, as well as the fabrication of semiconductor devicesthereon.

[0047] Referring now to FIGS. 7-11, a second shallow trench isolationstructure 30 embodiment of a semiconductor device structure according tothe present invention is illustrated. With reference to FIGS. 7 and 8,shallow trench isolation structure 30 includes a semiconductor substrate21 with a surface 22 and trenches 24 recessed, or formed in, surface 22.A layer of electrically nonconductive material, or insulator layer 36,substantially fills trenches 24 and covers surface 22. Insulator layer36 has a nonplanar upper surface 37 and includes valleys 34 locatedsubstantially above trenches 24 and peaks 32 located substantially abovesurface 22.

[0048] Shallow trench isolation structure 30 may also have a layer 38,38′ of stress buffer material, which is also referred to herein as astress buffer layer, having a substantially planar surface 39, 39′disposed at least partially over insulator layer 36. FIG. 7 illustratesstress buffer layer 38, which substantially fills valleys 34 recessed ininsulator layer 36 and substantially completely covers peaks 32. Thethickness T″ of regions of stress buffer layer 38 located above peaks 32is less than the depths D″ of valleys 34. Thickness T″ is preferablyless than about half of depth D″. FIG. 8 depicts stress buffer layer38′, which does not extend over peaks 32 and which may only partiallyfill valleys 34. Stress buffer layers 38, 38′ are preferably formed froma photoresist or other polymer by processes the same as or similar tothose disclosed previously herein with reference to the fabrication ofmask layer 18 illustrated in FIG. 2.

[0049] Once a substantially planar surface is formed over shallow trenchisolation structure 30, such as that formed at least partially bysurface 39 of stress buffer layer 38 and as illustrated in FIG. 7,stress buffer layer 38 and portions of insulator layer 36 located abovethe plane of surface 22 may be substantially concurrently removed. Forexample, layers 38 and 36 may be substantially removed by exposure tothe same etchant or combination of etchants that will remove stressbuffer layer 38 and insulator layer 36 at substantially the same ratesto provide the finished shallow trench isolation structure 30illustrated in FIG. 11. Either wet etchants or dry etchants may be used.Preferably, the use of etchants eliminates the formation ofimperfections or defects in surface 22 of semiconductor substrate 21, aswell as the possible introduction of contaminants or other debristhereon. Alternatively, known chemical-mechanical planarizationprocesses may be used to substantially concurrently remove stress bufferlayer 38 and portions of insulator layer 36 above surface 22, alsoproviding a finished shallow trench isolation structure 30 such as thatillustrated in FIG. 11. As stress buffer layer 38 provides asubstantially planar surface over shallow trench isolation structure 30,the likelihood that material of insulator layer 36 will be broken offduring the chemical-mechanical planarization process is reduced, therebyreducing the formation of imperfections or defects in surface 22, aswell as the creation of contaminants or other debris, which may occurduring chemical-mechanical planarization of a nonplanar surface.

[0050] As shown in FIG. 8, stress buffer layer 38′ may not provideshallow trench isolation structure 30 with a substantially planarsurface. Rather, peaks 32 of insulator layer 36 protrude above surface39′ of stress buffer layer 38′. In order to provide a substantiallyplanar surface over shallow trench isolation structure 30, the portionsof peaks 32 that protrude above the plane of surface 39′ may beselectively removed, such as by use of selective wet or dry etchprocesses. The material of peaks 32 that protrudes above the plane ofsurface 39′ is removed at least until a substantially planar surface 31is formed over shallow trench isolation structure 30, as depicted inFIG. 9.

[0051] As illustrated in FIG. 10, the selective removal of materialforming insulator layer 36 may continue until portions of insulatorlayer 36 located above the plane of surface 22 are substantiallyremoved. As a result, discontinuous quantities of stress buffer layer38′ remain above trenches 24 and the portions of insulator layer 36remaining therein. Stress buffer layer 38′ may be removed mechanicallyor by use of a wet or dry etchant that will not substantially remove orreact with the materials of semiconductor substrate 21 or of theportions of insulator layer 36 remaining within trenches 24. Forexample, if a photoresist is used to form stress buffer layer 38′, knownresist strippers may be used to remove stress buffer layer 38′ to form afinished shallow trench isolation structure 30, such as that illustratedin FIG. 11.

[0052] Alternatively, once a substantially planar surface 31 has beenformed over shallow trench isolation structure 30, as shown in FIG. 9,stress buffer layer 38′ and the portions of insulator layer 36 locatedabove the plane of surface 22 may be substantially concurrently removedfrom above shallow trench isolation structure 30 by use of one or moredry or wet etchants that remove the materials of layers 38 and 36 atsubstantially the same rates, as known in the art, or by knownchemical-mechanical planarization processes to provide the finishedshallow trench isolation structure 30 illustrated in FIG. 11.

[0053] Once a finished shallow trench isolation structure 30, such asthat depicted in FIG. 11, has been fabricated, one or more semiconductordevices may then be fabricated on shallow trench isolation structure 30,as known in the art.

[0054] FIGS. 12-16 illustrate yet another embodiment of a semiconductordevice structure 40 that incorporates teachings of the presentinvention. With reference to FIGS. 12 and 13, semiconductor devicestructure 40 includes dual damascene trenches 44 formed in a surface 42of an insulator layer 41 thereof. A conductive layer 46 overlies surface42 and substantially fills trenches 44. Conductive layer 46 has anonplanar upper surface 47 that includes valleys 54 locatedsubstantially over trenches 44 and peaks 52 located substantially oversurface 42. Insulator layer 41, trenches 44, and conductive layer 46, aswell as other structures of semiconductor device structure 40 underlyinginsulator layer 41 and trenches 44 are each fabricated by knownprocesses, such as those disclosed in U.S. Pat. No. 5,980,657 to Farraret al. on Nov. 9, 1999, the disclosure of which is hereby incorporatedin its entirety by this reference.

[0055] Semiconductor device structure 40 also includes a layer of stressbuffer material, which is also referred to herein as a stress bufferlayer 48, 48′, at least partially covering conductive layer 46 andhaving a substantially planar surface 49, 49′. FIG. 12 illustratesstress buffer layer 48, which substantially fills valleys 54 recessed inconductive layer 46 and substantially completely covers peaks 52. Thethickness T″′ of regions of stress buffer layer 48 located above peaks52 is less than the depths D″′ of valleys 54. Thickness T″′ ispreferably less than about half of depth D″′. FIG. 13 depicts stressbuffer layer 48′, which does not extend over peaks 52 and which may onlypartially fill valleys 54. Stress buffer layers 48, 48′ are preferablyformed from a photoresist or other polymer by processes the same as orsimilar to those disclosed previously herein with reference to thefabrication of mask layer 18 illustrated in FIG. 2.

[0056] Once a substantially planar surface is formed over semiconductordevice structure 40, such as that formed at least partially by surface49 of stress buffer layer 48 and as illustrated in FIG. 12, stressbuffer layer 48 and portions of conductive layer 46 located above theplane of surface 42 may be substantially concurrently removed. Forexample, layers 48 and 46 may be substantially concurrently removed withan etchant or combination of etchants that will remove stress bufferlayer 48 and insulator layer 46 at substantially the same rates toprovide the finished semiconductor device structure 40 illustrated inFIG. 16. Either wet etchants or dry etchants may be used. Preferably,the use of etchants eliminates the formation of imperfections or defectsin surface 42 of insulator layer 41, as well as the possibleintroduction of contaminants or other debris thereon. Alternatively,known chemical-mechanical planarization processes may be used tosubstantially concurrently remove stress buffer layer 48 and portions ofconductive layer 46 above surface 42, also providing a finishedsemiconductor device structure 40 such as that illustrated in FIG. 16.As stress buffer layer 48 provides a substantially planar surface overshallow trench isolation structure 40, the likelihood that material ofconductive layer 46 will be broken off during the chemical-mechanicalplanarization process is reduced, thereby reducing the formation ofimperfections or defects in surface 42, as well as the creation ofcontaminants or other debris, which may occur during chemical-mechanicalplanarization of a nonplanar surface.

[0057] As illustrated in FIG. 13, stress buffer layer 48′ may notprovide semiconductor device structure 40 with a substantially planarsurface. Rather, peaks 52 of conductive layer 46 protrude above surface49′ of stress buffer layer 48′. In order to provide a substantiallyplanar surface over semiconductor device structure 40, the portions ofpeaks 52 that protrude above the plane of surface 49′ may be selectivelyremoved, such as by use of selective wet or dry etch processes. Thematerial of peaks 52 that protrudes above the plane of surface 49′ isremoved at least until a substantially planar surface 51 is formed oversemiconductor device structure 40, as depicted in FIG. 14.

[0058]FIG. 15 illustrates that the selective removal of material formingconductive layer 46 may continue until portions of conductive layer 46located above the plane of surface 42 are substantially removedtherefrom. As a result, discontinuous quantities of stress buffer layer48′ remain above trenches 44 and the portions of conductive layer 46remaining therein. Stress buffer layer 48′ may be removed mechanicallyor by use of a wet or dry etchant that will not substantially remove orreact with the materials of insulator layer 41 or of the portions ofconductive layer 46 remaining within trenches 44. For example, if aphotoresist is used to form stress buffer layer 48′, known resiststrippers may be used to remove stress buffer layer 48′ to form asemiconductor device structure 40 such as that illustrated in FIG. 16.

[0059] Alternatively, once a substantially planar surface 51 has beenformed over semiconductor device structure 40, as shown in FIG. 14,stress buffer layer 48′ and the portions of conductive layer 46 locatedabove the plane of surface 42 may be substantially concurrently removedfrom above semiconductor device structure 40 by use of one or more wetor dry etchants that remove the materials of layers 48′ and 46 atsubstantially the same rates, as known in the art, or by known chemicalmechanical planarization processes to provide the semiconductor devicestructure 40 illustrated in FIG. 16.

[0060] Once a semiconductor device structure 40 such as that depicted inFIG. 16 has been fabricated, further known fabrication processes may beperformed.

[0061] Although the foregoing description contains many specifics, theseshould not be construed as limiting the scope of the present invention,but merely as providing illustrations of some of the presently preferredembodiments. Similarly, other embodiments of the invention may bedevised which do not depart from the spirit or scope of the presentinvention. Features from different embodiments may be employed incombination. The scope of the invention is, therefore, indicated andlimited only by the appended claims and their legal equivalents, ratherthan by the foregoing description. All additions, deletions andmodifications to the invention as disclosed herein which fall within themeaning and scope of the claims are to be embraced thereby.

What is claimed is:
 1. A semiconductor device structure with asubstantially planar surface, comprising: a substrate including at leastone recess formed therein; and a material layer disposed over saidsubstrate and substantially filling said at least one recess, saidmaterial layer having a substantially planar surface free of abrasiveplanarization-induced defects.
 2. The semiconductor device structure ofclaim 1, wherein said substrate comprises a semiconductor substrate witha surface and said at least one recess comprises at least one trenchrecessed in said surface of said semiconductor substrate.
 3. Thesemiconductor device structure of claim 1, wherein said material layercomprises a mask material.
 4. The semiconductor device structure ofclaim 3, further comprising at least one conductively doped regioncontinuous with a surface of said semiconductor substrate and laterallyadjacent said at least one trench.
 5. The semiconductor device structureof claim 1, wherein said substrate comprises: a shallow trench isolationstructure including a semiconductor substrate with a surface and atleast one trench formed in said surface of said semiconductor devicesubstrate; and an insulator layer substantially filling said at leastone trench and covering said surface of said semiconductor devicesubstrate.
 6. The semiconductor device structure of claim 5, whereinsaid insulator layer includes a nonplanar upper surface with at leastone peak located substantially above said surface of said semiconductordevice substrate and at least one valley located substantially abovesaid at least one trench.
 7. The semiconductor device structure of claim6, wherein said material layer comprises a stress buffer layer thatsubstantially fills said at least one valley in said insulator layer. 8.The semiconductor device structure of claim 1, wherein said substratecomprises: a semiconductor device structure including a surface with atleast one dual damascene trench formed thereon; and a conductive layersubstantially filling said at least one dual damascene trench andcovering said surface of said semiconductor device structure.
 9. Thesemiconductor device structure of claim 8, wherein said conductive layerincludes a nonplanar upper surface with at least one peak locatedsubstantially above said surface of said semiconductor device structureand at least one valley located substantially above said at least onedual damascene trench.
 10. The semiconductor device structure of claim9, wherein said material layer comprises a stress buffer layer thatsubstantially fills said at least one valley in said conductive layer.11. The semiconductor device structure of claim 1, wherein saidsubstrate comprises a stacked capacitor structure including an insulatorlayer with at least one container recessed therein.
 12. Thesemiconductor device structure of claim 11, wherein said material layercomprises a mask material, said mask material substantially filling saidat least one container.
 13. The semiconductor device structure of claim12, wherein mask material covering a surface of said insulator layer hasa thickness of less than a height of said at least one container. 14.The semiconductor device structure of claim 12, wherein mask materialcovering a surface of said insulator layer has a thickness of less thanabout half a depth of said at least one container.
 15. A semiconductordevice structure with a substantially planar surface, comprising: asubstrate including at least one recess formed therein; and a materiallayer disposed at least partially over said substrate so as to at leastpartially fill said at least one recess, said material layer having asubstantially planar surface substantially free of abrasiveplanarization-induced defects.
 16. The semiconductor device structure ofclaim 15, wherein at least one region of said substrate is exposedthrough said material layer.
 17. The semiconductor device structure ofclaim 15, further comprising: at least one intermediate layer betweensaid substrate and said material layer, at least one portion of saidintermediate layer at least partially filling said at least one recess.18. The semiconductor device structure of claim 17, wherein at least oneregion of said at least one intermediate layer is exposed through saidmaterial layer.
 19. The semiconductor device structure of claim 17,wherein said at least one intermediate layer comprises at least one of amask material, an insulative material, and a conductive material. 20.The semiconductor device structure of claim 15, wherein said materiallayer has a thickness that is less than a depth of said at least onerecess.